1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for the semiconductor device.
2. Description of the Related Art Conventionally, aluminum (Al) or an aluminum alloy is widely used as a material for wirings of a semiconductor device, while a silicon oxide (SiO2) film is widely used as a material for an interlayer insulating film of the semiconductor device. However, along with a progress in a finer pattern and higher speed of semiconductor devices, for improving a signal transmission delay in wirings, copper (Cu) having a lower resistance has become to be used as the material for wirings, whereas low dielectric constant film having lower dielectric constant such as an SiOCH film has become to be used as the insulating film.
In a case of forming Cu wirings, a dry etching process is difficult, and hence a damascene method is used in most cases. The damascene method includes steps of forming a groove in the insulating film formed on the semiconductor substrate, filling Cu in the groove, and polishing off excess Cu other than the wiring, thereby forming the Cu wiring.
Hereinafter, a common manufacturing method for the Cu wirings is described with reference to FIGS. 10 and 11.
FIG. 10A illustrates lower layer wirings on which upper layer wirings are to be formed. The lower layer wiring has a structure in which a cap insulating film 60a is formed on an SiOCH film 10a as the insulating film, and a Cu wiring 50a is filled in a wiring groove or a wiring hole having a barrier film 40a formed on the inner wall thereof. The lower layer wiring can be formed by the same process as the upper layer wiring that is described below.
First, as illustrated in FIG. 10B, an SiOCH film 10b is formed on the lower layer wiring. Next, as illustrated in FIG. 10C, using lithography and anisotropic etching, a wiring groove or a wiring hole is formed in the SiOCH film 10b. Next, as illustrated in FIG. 11A, a barrier film 40b that is a conductor film is formed in the wiring groove or the wiring hole, and further a Cu wiring 50b is filled in the wiring groove or the wiring hole. Next, using chemical mechanical polishing (CMP), excess Cu 50b and excess barrier film 40b outside the wiring groove or the wiring hole are removed (FIG. 11B). A cap insulating film 60b as an insulator is formed on the same, whereby a Cu wiring structure can be formed, which has the lower surface and the side surfaces covered with the barrier film 40b and the upper surface covered with the cap insulating film 60b as illustrated in FIG. 11C.
The SiOCH film 10 (10a and 10b) that is used as an insulating film between wires is a porous low dielectric constant film having a relative dielectric constant that is decreased to be 2.6 or lower by forming pores in the film for reducing parasitic capacitance between wires. However, the low dielectric constant film has characteristics of low mechanical strength and a hydrophobic surface. Therefore, if the low dielectric constant film is exposed in the CMP process for forming the Cu wirings by the damascene method, there may be a problem of film peeling or generation of particles or a watermark due to detergent deterioration.
In view of this problem, in order that the low dielectric constant film be protected, it is possible to form a hard mask made of an SiO2 or rigid low dielectric constant film having a relative dielectric constant without pores of approximately 3.0 on the low dielectric constant film.
Japanese Patent Application Laid-Open No. 2004-253790 (hereinafter, referred to as Patent Document 1) and Japanese Patent Application Laid-Open No. 2007-27347 (hereinafter, referred to as Patent Document 2) describe a semiconductor device in which the hard mask is formed on the low dielectric constant film as the interlayer insulating film of the Cu wiring structure.
Patent Document 1 describes a semiconductor device in which copper wirings are formed in an interlayer insulating film that is a lamination of a first SiOCH film, a second SiOCH film having C and H concentrations lower than those of the first SiOCH film and an O concentration higher than that of the first SiOCH film, and an SiO2 film, and further an SiCNH film is formed as an insulating film for preventing metal diffusion on the SiO2 film.
Patent Document 2 describes a semiconductor device in which wirings are formed in the interlayer insulating film including a porous low dielectric constant film and a hard mask, and, e.g., a silicon carbide (SiC) film is further formed as an antioxidant film layer on the hard mask layer. This hard mask is made of a silicon oxide (SiO2).
However, according to the semiconductor device described in Patent Document 1, a silicon oxide (SiO2) film having a high dielectric constant is formed on the first SiOCH film and the second SiOCH film that are used as the low dielectric constant film. In addition, according to the semiconductor device described in Patent Document 2, the hard mask made of a silicon oxide (SiO2) having a high dielectric constant is formed on the porous low dielectric constant film. Therefore, in each of the semiconductor devices described in Patent Documents 1 and 2, if there is a structure for protecting the interlayer insulating film having a low dielectric constant by the hard mask or the like, the dielectric constant of the interlayer insulating film is increased.